darshankabariya

Extended a verilog compiler front end (UDPs, loops, blocks) and advanced static elaboration for RTL designs, implementing semantics defined by the language standard; contributed improvements to the open-source Slang compiler. Built a translation unit that walks compiler-generated ASTs and transfers design semantics into an object-oriented database, enabling data sharing between simulation and verification services in an EDA toolchain. Built a UPF-driven low-power simulation flow from the ground up, including static elaboration and integration of low-power semantics. Debugged and profiled simulator correctness and performance issues across a large C++ codebase using GDB, adding regression tests to lock in fixes.