juanma

Integrated and verified low-latency FPGA networking IP (Ethernet UDP/IP) core, optimizing for high-throughput communication and providing PL networking capabilities, including direct PL-PS data bridging and modification of Linux drivers for network sockets to interact with higher OSI layers of the DDS protocol. Performed real HW tests including SFP interconnection, round-trip benchmarking and monitoring of traffic with Wireshark. Successfully integrated, simulated, and tested FPGA implementations for real-time ROS and RTPS capabilities, achieving up to 100x speed-up ratios wrt SW implementations. Configured and utilized Alveo U25 cards, leveraging their high-bandwidth networking and PCIe capabilities for efficient Linux host interaction. Accelerated robotics and computer vision tasks (e.g., video obstacle detection, downsampling) using Vitis HLS to offload processing from CPUs and handling FPGA-host communication via PCIe, significantly improving performance. Developed comprehensive data acquisition systems for analog signals via ADCs and parallel pins, including post-processing, Ethernet communication to workstations, and data visualization (Python, Rerun). Key Technologies: AMD FPGAs, VHDL, Verilog, Vitis HLS, AXIS, Zynq MPSoC, KR260, XRT, Vivado/Vitis suite, cocotb, git, Make, Python.

Implemented VHDL and Verilog designs focused on high-speed video streaming, bridging (e.g., parallel to MIPI CSI), and aggregation, emphasizing data path optimization. Utilized AXI Stream as the primary intermediate protocol for efficient data transfer. Integrated and configured Lattice dphy, PLLs, clock muxes, and other IPs for complex designs. Applied stringent physical and timing constraints to ensure design integrity and meet performance targets. Integrated proper CDC techniques. Conducted thorough simulation and verification using Modelsim, Tcl automation, VUnit, and IP simulation, ensuring robust and error-free designs.

Conducted in-depth research on complex multicore SoC (MPSoC) architectures (Zynq UltraScale+, T2080, LX2160A) to understand and mitigate data path contention. Leveraged AXI Traffic Generators (ATG) to analyze, track, and stress data paths within Zynq UltraScale+ systems. Designed and implemented a custom VHDL core for an AXI traffic generator, enabling efficient memory access and register-level customization from the ARM core via a C driver. Co-authored the publication "Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC". Developed baremetal C and assembly microbenchmarks to stress various interference channels on target platforms (PPC T2080; ARM LX2160A).