wilberthgm

Designed and integrated datapath and control logic for a 6-stage pipelined RISC-V SoC from the Hardware Architecture Specification (HAS); resolved structural hazards via forwarding and stall logic, validated on FPGA (AMD Vivado). Implemented arithmetic and arbitration logic for the RISC-V SoC, including the ALU datapath and a round-robin arbiter for shared-resource access. Validated RISC-V SoC functionality on FPGA (AMD Vivado, Basys-3) at 100 MHz using hand-written RISC-V assembly self-checking tests, exposing hardware-level bugs not caught in simulation. Co-authored verification test plans mapping 100% of design features to functional coverage points, driving root-cause resolution of failing RTL tests and reducing pre-sign-off defect escapes. Implemented UVM regression flows with reference-model verification, enabling instruction-level comparison between RTL execution and the RISC-V architectural golden model to detect functional mismatches across datapath, control logic, pipeline, memory, and CSR/trap scenarios. Developed and maintained a reusable UVM verification environment for a pipelined RISC-V VLSI SoC, integrating agents, monitors, scoreboards, drivers, sequencers, functional coverage collectors, and transaction-level communication through UVM analysis ports. Debugged RTL and UVM failures using VCS and Vivado, analyzing waveforms, transaction-level logs, Spike ISS traces, and pipeline state transitions to resolve critical design bugs before FPGA validation. Enforced design integrity for physical implementation by driving SpyGlass lint closure across structural, coding-style, and synthesizability categories, preventing downstream rework in synthesis and SoC integration. Built local, self-hosted LLM-assisted Python and Shell automation scripts to run UVM regressions against the reference model and Spike ISS for RISC-V environments, accelerating the feedback loop across RTL iterations. Maintained GitHub as the single source of truth for design status on a RISC-V SoC project, running pre-PR regression checks and issue-tracking workflows; reported progress and blockers to project leads in structured status reviews.

Refactored and standardized RTL for a custom multicycle RISC-V processor across datapath, control logic, and general-purpose/CSR register subsystems, ensuring behavioral adherence to the specification and synthesis readiness for downstream FPGA prototyping. Verified processor correctness via co-simulation against an ISS golden reference model, using a memory-array-based self-checking UVM scoreboard to resolve corner-case instruction and CSR behavior bugs. Applied SpyGlass static analysis and simulation-based debug against a reference model to resolve 50+ lint, CDC, synthesizability, and functional issues across RTL change iterations. Ran logic synthesis on the standardized RISC-V processor using Synopsys Fusion Compiler, analyzing power, area, and timing reports to evaluate the RTL implementation. Architected a complete UVM environment from scratch for a UART DUT: reusable agents, sequencers, drivers, monitors, scoreboards, coverage collectors, uvm_sequence/uvm_sequence_item transaction classes, constrained-random stimulus, uvm_config_db configuration, and SVA protocol checks. Achieved 95%+ functional coverage and 100% code coverage on targeted UART DUT blocks by analyzing VCS coverage reports, identifying coverage holes, and closing them with additional directed and constrained-random scenarios. Verified UART DUT behavior against the Microarchitecture Specification (MAS), achieving coverage closure with zero unresolved protocol violations.