Findora Internship

Reporting to the Manager, Engineering (ASIC/FPGA), the Master's intern will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high speed crypto applications. S/he will implement high speed crypto architectures, on ASICs / Xilinx FPGAs. S/he will be responsible for reading engineering specifications from system requirements, detailed architecture, design (RTL, HLS (C++ to RTL)) and RTL quality (CDC, Formal, Lint), Test plans, module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards, Silicon/FPGA bring up, characterization and production support/collateral.

*Start Date: Jan 2022 *Duration: 6 months - with a chance to convert to full-time and H1B sponsorship *This position is located in the bay area. No remote. Only apply if you live in the area or are willing to relocate.