Bitfury is hiring a

Web3 RTL Verification Engineer

Duties and responsibilities:

• Functional verification planning and test-plan development.
• Guarantee RTL designs are matching specifications and requirements.
• Define and implement verification plans, coverage nodes and test plans to ensure the designs meet quality and performance goals.
• Build and maintain automated verification environments.
• Collaborate and communicate with management regarding verification status, project progress, and issue resolution.
• Triage and debug of design failures, coverage development and closure.
• Provide proper and comprehensive documentation for the usage and the architecture of the verification environments as well as reports for the verification results.
• Contribute to technical directions on all aspects of the verification domain.
• Ability to work closely with digital/analog designers to support both pre and post silicon verification efforts.

Qualification:

• 12+ years of experience in UVM/OVM: defining test methodologies, test plans, and test benches.
• Design verification EDA tools like VCS, VSIM.
• Test plan and test development experience (in UVM, C/C++, System Verilog).
• Knowledge of System Verilog Assertions and functional coverage.
• Data management and version control systems.
• Proficiency in programming and/or scripting languages (Perl, Python, Cshell…).
• Background in digital circuitry or hardware logic design.