Bitfury Jobs in United States
There are 31 Web3 Jobs at Bitfury
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Job Position | Company | Posted | Location | Salary | Tags |
---|---|---|---|---|---|
Bitfury | San Francisco, CA, United States | $54k - $90k | |||
Bitfury | Sacramento, CA, United States | $54k - $90k | |||
Bitfury | San Jose, CA, United States | $54k - $90k | |||
Bitfury | Sacramento, CA, United States | $72k - $75k | |||
Learn job-ready web3 skills on your schedule with 1-on-1 support & get a job, or your money back. | | by Metana Bootcamp Info | |||
Bitfury | San Jose, CA, United States | $72k - $75k | |||
Bitfury | San Francisco, CA, United States | $72k - $75k | |||
Bitfury | Austin, TX, United States | $54k - $100k | |||
Bitfury | Washington, United States | $23k - $35k | |||
Bitfury | Austin, TX, United States | $23k - $35k | |||
Bitfury | New York, NY, United States | $23k - $35k | |||
Bitfury | Boston, MA, United States | $50k - $80k | |||
Bitfury | Austin, TX, United States | $50k - $80k | |||
Bitfury | New York, NY, United States | $50k - $80k | |||
Bitfury | Boston, MA, United States | $45k - $80k | |||
Bitfury | Austin, TX, United States | $45k - $80k |
Bitfury
$54k - $90k estimated
This job is closed
We are currently searching for an RTL Verification Engineer to join our ASIC development team.
Duties and responsibilities:
- Functional verification planning and test-plan development.
- Guarantee RTL designs are matching specifications and requirements.
- Define and implement verification plans, coverage nodes and test plans to ensure the designs meet quality and performance goals.
- Build and maintain automated verification environments.
- Collaborate and communicate with management regarding verification status, project progress, and issue resolution.
- Triage and debug of design failures, coverage development and closure.
- Provide proper and comprehensive documentation for the usage and the architecture of the verification environments as well as reports for the verification results.
- Contribute to technical directions on all aspects of the verification domain.
- Ability to work closely with digital/analog designers to support both pre and post silicon verification efforts.
Qualification:
- 12+ years of experience in UVM/OVM: defining test methodologies, test plans, and test benches.
- Design verification EDA tools like VCS, VSIM.
- Test plan and test development experience (in UVM, C/C++, System Verilog).
- Knowledge of System Verilog Assertions and functional coverage.
- Data management and version control systems.
- Proficiency in programming and/or scripting languages (Perl, Python, Cshell…).
- Background in digital circuitry or hardware logic design.